A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver

This paper presents a 12-bit 750KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for wireless portable device. The scheme of the ADC is based on a Dual-Sampling Capacitive DAC technique, low power dynamic latch comparator with Adaptive Power Control (APC) and bootstrap switch to reduce chip area and power consumption. The proposed 12-bit dual sampling CDAC topology reduces switching energy-efficient compared with 12-bit conventional SAR ADC. The prototype SAR ADC was implemented in Dongbu HiTek 0.18μm CMOS technology and occupies 0.68 mm2. The post-layout simulation results show the proposed ADC achieves an ENOB of 11.196 bit at a sampling frequency 750KS/s. It consumes only 0.48mW from a 5.0V supply and achieves the INL and DNL +1.45/-0.65 LSB and +1.0/-1.0 LSB respectively, SNDR 69.16dB, SFDR 78.18dB, and figure of merit (FoM) of 273 fJ/conversion-step.