AN NOVEL VLSI ARCHITECTURE FOR URDHVA TIRYAKBHYAM VEDIC MULTIPLIER USING EFFICIENT CARRY SELECT ADDER

In the design of integrated circuits, area plays a vital role because of increasing the necessity of portable systems. CSLA is a fast adder used in many data processing processors for performing fast arithmetic functions. In this paper 4bit, 8bit, 16bit, 32bit, 64bit and 128 bit CSLA have been developed and applied in 4x4 bit, 8x8 bit, 16x16 bit, 32x32 bit, 64x64 bit and 128x128 bit Vedic multiplier respectively. This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance.Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros. The regular CSLAconsumes more areaand hence modified linear CSLA is used which requires less area. For simulating the CSLA’s and Vedic multipliers using CSLA’s.ISIM simulator is used. Further, the Verilog HDL coding of 128x128 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done and output has been displayed on LCD of Spartan 3E kit.