FPGA Implementation of Predictive Cascaded Speed and Current Control of PMSM Drives With Two-Time-Scale Optimization

This paper proposes a field programmable gate array (FPGA) implementation of predictive speed and current control of permanent magnet synchronous motor (PMSM) with two-time-scale optimization. Considering the time-scale characteristics of speed loop and current loop, different sampling times are assigned to the subsystems. The predictions of both slow and fast models consuming great computation resource for all the prediction instants are analyzed in two-time-scale system. In order to achieve a fast and accurate predictive control, the proposed method is implemented on an FPGA. Parallel unrolling and maximized parallel pipeline architecture are designed specifically to optimize the computational time of the proposed method. Experimental results validated in PMSM drives illustrate that proposed implementation achieves a high performance with balanced resource consumption.