Combining multiple DFT schemes with test generation
暂无分享,去创建一个
[1] S.M. Reddy,et al. On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[2] Parker,et al. Design for Testability—A Survey , 1982, IEEE Transactions on Computers.
[3] Janak H. Patel,et al. A fault oriented partial scan design approach , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[4] L. H. Goldstein,et al. Controllability/observability analysis of digital circuits , 1978 .
[5] D. G. Saab,et al. Partial Reset: An Alternative DFT Approach , 1994 .
[6] Robert C. Aitken,et al. THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%? , 1991, 1991, Proceedings. International Test Conference.
[7] Janak H. Patel,et al. HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..
[8] H. T. Nagle,et al. Design for testability and built-in self test: a review , 1989 .
[9] Irith Pomeranz,et al. Test generation for synchronous sequential circuits using multiple observation times , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.
[10] Prathima Agrawal,et al. CONTEST: a concurrent test generator for sequential circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[11] Ben Mathew. Enhancing testability of VLSI circuits using partial reset techniques , 1995 .
[12] R. Gupta,et al. Configuring multiple scan chains for minimum test time , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[13] K.-T. Cheng,et al. A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.
[14] Irith Pomeranz,et al. Classification of Faults in Synchronous Sequential Circuits , 1993, IEEE Trans. Computers.
[15] J.H. Patel,et al. Probe point insertion for at-speed test , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.
[16] Miron Abramovici,et al. A Cost-Based Approach to Partial Scan , 1993, 30th ACM/IEEE Design Automation Conference.
[17] Alberto L. Sangiovanni-Vincentelli,et al. Irredundant sequential machines via optimal logic synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] M.S. Abadir. TIGER: testability insertion guidance expert system , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[19] Daniel G. Saab,et al. Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Irith Pomeranz,et al. On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation , 1994, IEEE Trans. Computers.
[21] D. G. Saab,et al. Partial reset: An inexpensive design for testability approach , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[22] Daniel G. Saab,et al. On selecting flip-flops for partial reset , 1993, Proceedings of IEEE International Test Conference - (ITC).
[23] Masahiro Fujita,et al. A fast test pattern generation for large scale circuits , 1993 .
[24] Vishwani D. Agrawal,et al. State assignment for initializable synthesis (gate level analysis) , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[25] Alberto L. Sangiovanni-Vincentelli,et al. An incomplete scan design approach to test generation for sequential machines , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[26] James B. Angell,et al. Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.
[27] Kazumi Hatayama,et al. Sequential test generation based on real-valued logic simulation , 1992, Proceedings International Test Conference 1992.
[28] Kang G. Shin,et al. Design for test using partial parallel scan , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[29] Vishwani D. Agrawal,et al. Initializability Consideration in Sequential Machine Synthesis , 1992, IEEE Trans. Computers.
[30] Miron Abramovici,et al. On combining design for testability techniques , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[31] Rabindra K. Roy,et al. The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.
[32] F. Brglez,et al. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .
[33] Vishwani D. Agrawal,et al. STATE ASSIGNMENT FOR INITIALIZABLE SYNTHESIS , 1989 .
[34] R. D. Hess. Considerations in selecting a design-for-testability technique , 1988, IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'.
[35] Miron Abramovici,et al. One-pass redundancy identification and removal , 1992, Proceedings International Test Conference 1992.
[36] Arthur D. Friedman,et al. Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.
[37] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[38] Charles R. Kime,et al. Partial scan using reverse direction empirical testability , 1993, Proceedings of IEEE International Test Conference - (ITC).
[39] T. Gheewala,et al. CrossCheck: A Cell Based VLSI Testability Solution , 1989, 26th ACM/IEEE Design Automation Conference.
[40] Elizabeth M. Rudnick,et al. Non-Scan Design-for-Testability Techniques for Sequential Circuits , 1993, 30th ACM/IEEE Design Automation Conference.
[41] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[42] Toshinobu Ono,et al. A test generation method for sequential circuits based on maximum utilization of internal states , 1991, 1991, Proceedings. International Test Conference.
[43] K. S. Kim,et al. Partial scan by use of empirical testability , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[44] Elizabeth M. Rudnick,et al. Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation , 1995, 32nd Design Automation Conference.
[45] Kwang-Ting Cheng,et al. Timing-driven partial scan , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.