SEAS: a system for early analysis of SoCs
暂无分享,去创建一个
Subhrajit Bhattacharya | Nagu R. Dhanwada | Youngsoo Shin | Reinaldo A. Bergamaschi | Indira Nair | John A. Darringer | William E. Dougherty | Sarala Paliwal | S. Bhattacharya | Youngsoo Shin | R. Bergamaschi | N. Dhanwada | W. Dougherty | I. Nair | J. Darringer | S. Paliwal
[1] Rajesh Gupta,et al. Design planning for high-performance ASICs , 1996, IBM J. Res. Dev..
[2] D. Sciuto,et al. System-level performance estimation strategy for sw and hw , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).
[3] Luca Benini,et al. System-level power estimation and optimization , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).
[4] J. Madsen,et al. A unified component modeling approach for performance estimation in hardware/software codesign , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).
[5] Srinivas Devadas,et al. A methodology for accurate performance evaluation in architecture exploration , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).
[6] Jean-Marc Daveau,et al. Automating the Design of SOCs Using Cores , 2001, IEEE Des. Test Comput..
[7] Daniel Brand,et al. Early analysis tools for system-on-a-chip design , 2002, IBM J. Res. Dev..
[8] Luciano Lavagno,et al. Cosimulation-based power estimation for system-on-chip design , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[9] Thorsten Grotker,et al. System Design with SystemC , 2002 .