论文信息 - Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates

Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates

A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This ki ...

[1] S. Thompson. MOS Scaling: Transistor Challenges for the 21st Century , 1998 .

[2] E. E. Jones,et al. Shallow junction doping technologies for ULSI , 1998 .

[3] Toshitsugu Sakamoto,et al. Transistor characteristics of 14-nm-gate-length EJ-MOSFETs , 2000 .

[4] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .

[5] John R. Hauser,et al. Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? , 2002, IBM J. Res. Dev..

[6] W. Henschel,et al. Sub-10 nm linewidth and overlay performance achieved with a fine-tuned EBPG-5000 TFE electron beam lithography system , 2000, Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387).

[7] Toshitsugu Sakamoto,et al. Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors , 2000 .

[8] W. Fichtner,et al. Generalized guide for MOSFET miniaturization , 1980, IEEE Electron Device Letters.