论文信息 - The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth's algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs

[1] Hans Jürgen Mattausch,et al. A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features , 2005, IEICE Trans. Electron..

[2] Shorin Kyo,et al. ISSCC 2003 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER 2.6 2.6 A 51.2GOPS Scalable Video Recognition Processor for Intelligent Cruise Control Based on a Linear Array of 128 4-Way VLIW Processing Elements , 2001 .

[3] T. Gyohten,et al. The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture , 2006, VLSIC 2006.

[4] K. Fujishima,et al. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture , 2005, IEEE Journal of Solid-State Circuits.

[5] J.B. Kuang,et al. A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[6] K. Dosaka,et al. A 40GOPS 250mW massively parallel processor based on matrix architecture , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[7] B. Flachs,et al. A streaming processing unit for a CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..