Precise final state determination of mismatched CMOS latches
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[1] J.-H. Chang,et al. A BiCMOS 50 MHz cache controller for a superscalar microprocessor , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2] Takayasu Sakurai,et al. Delay analysis of series-connected MOSFET circuits , 1991 .
[3] A. Albicki,et al. Analysis of mesastable operation in RS CMOS flip-flops , 1987 .
[4] J. Navarro,et al. Metastability behavior of mismatched CMOS flip-flops using state diagram analysis , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[5] K. Natori. Sensitivity of dynamic MOS flip-flop sense amplifiers , 1986, IEEE Transactions on Electron Devices.
[6] Lee-Sup Kim,et al. Metastability of CMOS latch/flip-flop , 1990 .
[7] Jieh-Tsorng Wu,et al. A 100-MHz pipelined CMOS comparator , 1988 .
[8] R.K. Cavin,et al. CMOS sampler with 1 Gbit/s bandwidth and 25 ps resolution , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[9] John L. Wyatt,et al. Mismatch sensitivity of a simultaneously latched CMOS sense amplifier , 1991 .