Harmonic balance device analysis of an LDMOS RF power amplifier with parasitics and matching network

This paper discusses a harmonic balance simulation involving a high power LDMOS device, bias circuitry and matching network. The paper begins with a discussion of the device and circuit configuration as well as the requirements for simulation. Next the paper describes the simulation algorithms and simulator structure in order to meet the requirements. PISCES is used as the basis and around it are added libraries for harmonic balance simulation and circuit boundary conditions. Finally, simulation results are presented. The experimental and simulated response of the power gain and power added efficiency of an RF power amplifier are shown.