A 50 Gb / s CMOS Crossbar Chip using Asymmetric Serial Links *

A synchronous crossbar chip was designed in a 0.27µm CMOS technology for use in a high-speed network switch [1]. The crossbar chip uses 32 Asymmetric Serial Links [2] [3] to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexors with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is < 10-14 when all channels and the switch core are operating. The crossbar chip consumes 5W and provides a total bandwidth above 50 Gb/s. Architecture Crossbar switches are increasingly used for high capacity network switches [1]. Using high-speed serial links for the I/O interface of a crossbar switch chip can reduce the number of I/O pins required to provide a given bandwidth. A crossbar chip, which has many links converging on it, tends to be large and power-hungry because of the silicon area and power consumed by the timing circuits (usually PLLs) and transceivers. To reduce both power and area, we used Asymmetric Serial Links, which adjust the transmitter and receiver clocks on the port chips (the Smart End of the link) while leaving the clocks on the crossbar chip (the Dumb End) fixed. Each crossbar chip interfaces with as many as 32 network port chips in our design. Figure 1: Chip architecture of the crossbar Figure 1 shows the physical architecture of the crossbar chip, which consists of 32 Asymmetric Serial Links, a PLL, an 800MHz clock distribution tree (not shown), a switch core, and a crossbar controller. The speed of the pin interface is 1.6 Gb/s. The switch core and the majority of the digital logic on the chip runs at 200MHz. The speed conversion between these two clock domains is handled by serial-to-parallel and parallel-to-serial converters inside the Asymmetric Serial Links. 200MHz is 1/8 of the bit rate of the serial links and hence all the datapaths on the chip are 8 bits wide, including the switch core and the interface registers between the serial links and the switch core. The PLL serves two purpose. First is for clock multiplication. Second is to compensate for delay variations in the clock distribution. During normal operations, all 32 serial link blocks work as Dumb Ends of the Asymmetric Serial Links, which do not adjust their own transmitter and receiver clocks. However, for testing purposes, two serial link blocks …