A Floorprint-Based Defect Tolerance for Nano-Scale Application-Specific IC

A floorprint-based yield modeling, assurance and optimization method for the defect tolerant NASIC system under broken nanowire (NW) defects has been proposed in a short version of this paper, and the proposed models and methods are further validated and demonstrated through extensive parametric simulations in this paper. A yield model for each defect tolerant NASIC technique is developed based on the nature of the defects of concern in a floorprint-based analysis, thereby establishing an adequate foundation to evaluate and optimize the manufacturing process and defect tolerance by providing a capability to take into account the effect of each individual defect tolerance technique or synergetic effect of various combinations of the techniques on the overall expected yield of the product. According to the simulation results given in this paper, the defect tolerant NASIC system with 15 row and column NWs, respectively, each with length = 0.000034 on horizontal and vertical core nanoarray in a nanotile can achieve a yield higher than 99.8%. Ultimately, intelligent exploitation of the proposed yield modeling and simulation methods will make possible to realize a reliable NASIC-based computing system.

[1]  Minsu Choi,et al.  Modeling yield of carbon-nanotube/silicon-nanowire FET-based nanoarray architecture with h-hot addressing scheme , 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

[2]  C. Dekker,et al.  Logic Circuits with Carbon Nanotube Transistors , 2001, Science.

[3]  Minsu Choi,et al.  Modeling yield of carbon-nanotube/silicon-nanowire FET-based nanoarray architecture with h-hot addressing scheme , 2004 .

[4]  Charles M. Lieber,et al.  Logic Gates and Computation from Assembled Nanowire Building Blocks , 2001, Science.

[5]  Z. Patitz,et al.  A Floorprint-based Defect Tolerance for Nano-scale Application-Specific IC , 2008, 2008 IEEE Instrumentation and Measurement Technology Conference.

[6]  A STUDY ON THE YIELD OF SELF-HEALING CARBON NANOTUBE/NANOWIRE-BASED SYSTEM By JONGHO SEOL , 2005 .

[7]  Charles M. Lieber,et al.  High Performance Silicon Nanowire Field Effect Transistors , 2003 .

[8]  Csaba Andras Moritz,et al.  Wire-Streaming Processors on 2-D Nanowire Fabrics , 2005 .

[9]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.

[10]  A. DeHon.  Array-Based Architecture for Molecular Electronics , 2001 .

[11]  C. Moritz,et al.  Self-Healing Wire-Streaming Processors on 2-D Semiconductor Nanowire Fabrics , 2006 .

[12]  Charles M. Lieber,et al.  Functional nanoscale electronic devices assembled using silicon nanowire building blocks. , 2001, Science.

[13]  C. Moritz,et al.  Towards Defect-Tolerant Nanoscale Architectures , 2006, 2006 Sixth IEEE Conference on Nanotechnology.

[14]  Robert E. Lyons,et al.  The Use of Triple-Modular Redundancy to Improve Computer Reliability , 1962, IBM J. Res. Dev..

[15]  Charles M. Lieber,et al.  Carbon nanotube-based nonvolatile random access memory for molecular computing , 2000, Science.

[16]  R. Martel,et al.  Carbon nanotube field-effect transistors and logic circuits , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[17]  Teng Wang,et al.  Latching on the wire and pipelining in nanoscale designs , 2004 .

[18]  André DeHon,et al.  Array-Based Architecture for FET-Based, , 2003 .

[19]  Charles M. Lieber,et al.  Growth and transport properties of complementary germanium nanowire field-effect transistors , 2004 .

[20]  Teng Wang,et al.  Opportunities and challenges in application-tuned circuits and architectures based on nanodevices , 2004, CF '04.

[21]  D. Strukov,et al.  CMOL: Devices, Circuits, and Architectures , 2006 .

[22]  Charles M. Lieber,et al.  Directed assembly of one-dimensional nanostructures into functional networks. , 2001, Science.

[23]  C. Lieber,et al.  Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems , 2003, Science.