Ultra-thin chip technology and applications, a new paradigm in silicon technology

Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the related applications represent a new paradigm in silicon technology. The paper highlights the prominent applications of ultra-thin chips, alerts to the related technological issues and compares the candidate enabling technologies.

[1]  K.E. Petersen,et al.  Silicon as a mechanical material , 1982, Proceedings of the IEEE.

[2]  V.P. Ganesh,et al.  Overview and Emerging Challenges in Wafer Thinning Process for Handheld Applications , 2006, 2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium.

[3]  U. Zschieschang,et al.  Flexible organic complementary circuits , 2005, IEEE Transactions on Electron Devices.

[4]  Karlheinz Bock,et al.  Investigations of the influence of dicing techniques on the strength properties of thin silicon , 2007, Microelectron. Reliab..

[5]  Sigurd Wagner,et al.  Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates , 2002 .

[6]  W. Appel,et al.  A New Fabrication and Assembly Process for Ultrathin Chips , 2009, IEEE Transactions on Electron Devices.

[7]  H. Klauk,et al.  Ultralow-power organic complementary circuits , 2007, Nature.

[8]  Sung Kyu Park,et al.  Polymeric Substrate Spin-Cast diF-TESADT OTFT Circuits , 2008, IEEE Electron Device Letters.

[9]  H. Klauk,et al.  Fast organic thin-film transistor circuits , 1999, IEEE Electron Device Letters.

[10]  Gabor Karsai,et al.  Smart Dust: communicating with a cubic-millimeter computer , 2001 .

[11]  Ute Zschieschang,et al.  Low-voltage organic thin-film transistors with large transconductance , 2007 .

[12]  Payman Zarkesh-Ha,et al.  Global interconnect design in a three-dimensional system-on-a-chip , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[14]  Jin Jang,et al.  Dynamic characteristics of MICC polycrystalline thin film transistors , 2006 .

[15]  M. Koyanagi,et al.  Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections , 2006, IEEE Transactions on Electron Devices.

[16]  Andrew A. Wereszczak,et al.  Probabilistic strength of {1 1 1} n-type silicon , 2000 .

[17]  Payman Zarkesh-Ha,et al.  Interconnect opportunities for gigascale integration , 2002, IBM J. Res. Dev..

[18]  H. Reichl,et al.  Ultra thin chips for miniaturized products , 2001, First International IEEE Conference on Polymers and Adhesives in Microelectronics and Photonics. Incorporating POLY, PEP & Adhesives in Electronics. Proceedings (Cat. No.01TH8592).

[19]  P. Zarkesh-Ha,et al.  A global interconnect design window for a three-dimensional system-on-a-chip , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[20]  V. Gupta,et al.  Experimental evaluations of the strength of silicon die by 3-point-bend versus Ball-on-Ring tests , 2009, 2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

[21]  Y. Mishima,et al.  High-performance CMOS circuits fabricated by excimer-laser-annealed poly-Si TFTs on glass substrates , 2001, IEEE Electron Device Letters.

[22]  A. A. Wereszczak Probabilistic Strength of {111} N-Type Silicon , 2000 .

[23]  Karlheinz Bock,et al.  Polymer Electronics Systems - Polytronics , 2005, Proceedings of the IEEE.