Delay defect diagnosis methodology using path delay measurements

With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.

[1]  Sani R. Nassif,et al.  Efficient and product-representative timing model validation , 2011, 29th VLSI Test Symposium.

[2]  Kwang-Ting Cheng,et al.  Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step , 2003, DATE.

[3]  Janak H. Patel,et al.  Bounding circuit delay by testing a very small subset of paths , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[4]  Patrick Girard,et al.  A novel approach to delay-fault diagnosis , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[5]  Ying-Yen Chen,et al.  Diagnosis Framework for Locating Failed Segments of Path Delay Faults , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Malgorzata Marek-Sadowska,et al.  Delay-fault diagnosis using timing information , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Malgorzata Marek-Sadowska,et al.  Delay-fault diagnosis using timing information , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Ying-Yen Chen,et al.  Diagnosis framework for locating failed segments of path delay faults , 2005, IEEE International Conference on Test, 2005..

[9]  Kwang-Ting Cheng,et al.  Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[10]  Nur A. Touba,et al.  A systematic approach for diagnosing multiple delay faults , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[11]  Ying-Yen Chen,et al.  A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities , 2009, 2009 Asian Test Symposium.

[12]  Shi-Yu Huang,et al.  Gate-delay fault diagnosis using the inject-and-evaluate paradigm , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[13]  Sandeep K. Gupta,et al.  A new path-oriented effect-cause methodology to diagnose delay failures , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  Nur A. Touba,et al.  Adaptive techniques for improving delay fault diagnosis , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).