Aspects of dynamically reconfigurable logic

Field programmable logic has thrived by offering an alternative technology for the realisation of conventional digital systems. The combination of user programmability, and rapidly increasing levels of logic integration and operating speeds, explains the continued success of field programmable devices. Reconfigurable logic, and especially dynamically reconfigurable logic, are categories of field programmable logic that can be used to extend the design space to create digital systems with distinctly new characteristics. This paper adopts a broad perspective on dynamically reconfigurable logic. It presents the current state-of-the-art before identifying and classifying the principal challenges that must be overcome if dynamically reconfigurable logic is to be exploited successfully. FPGAs are interpreted as one class of array architectures and the experiences of development with previous array architectures are assessed in the context of dynamically reconfigurable logic. The dominant role of the von Neumann, stored program computer as the principal model for programmable systems and its sometimes detrimental effect on research into dynamically reconfigurable logic are discussed. The design process for dynamically reconfigurable logic requires that logical and physical design perspectives be considered simultaneously. This has been at odds with established design methodologies for mask programmed ASICs and FPGAs. However, with the advent of deep sub-micron ASICs, the need to couple logical and physical design more closely is now clearly recognised and is further reinforced by the move towards design re-use of intellectual property in the era of system on chip. Since design tools for mask programmed ASICs heavily influence tools for FPGAs, this trend is evaluated in the context of the development of dynamically reconfigurable logic. Finally, the paper offers a conjecture for the future of reconfigurable logic. (5 pages)