A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors

The advancement of Silicon CMOS technology has led information technology innovation for decades. However, scaling transistors down according to Moore’s law is almost reaching its limitations. To improve system performance, cost, and energy efficiency, vertical-optimization in multiple layers of the computing stack is required. Technological awareness in terms of devices and circuits could enable informed system-level decisions. For example, graphene is a promising material for extremely scaled high-speed transistors because of its remarkably high mobility, but it can not be used in integrated circuits as a result of the high leakage current from its zero bandgap. In this article, we discuss the fundamental physics of transistors and their ramifications on system design to assist device-level technology consideration during system design. Additionally, various emerging devices and their utilization on a vertically-optimized computing stack are introduced. This article serves as a survey of emerging device technologies that may be relevant in these areas, with an emphasis on making the descriptions approachable by system and software designers to understand the potential solutions. A basic vocabulary will be built to understand how to digest technical content, followed by a survey of devices, and finally a discussion of the implications for future processing systems.

[1]  Ahmad Ehteshamul Islam,et al.  Variability and Reliability of Single-Walled Carbon Nanotube Field Effect Transistors , 2013 .

[2]  Yang Li,et al.  Effect of Ferroelectric Damping on Dynamic Characteristics of Negative Capacitance Ferroelectric MOSFET , 2016, IEEE Transactions on Electron Devices.

[3]  Wei D. Lu,et al.  Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor. , 2016, Nano letters.

[4]  Md Maksudul Hossain,et al.  DC Modeling and Geometry Scaling of SiC Low-Voltage MOSFETs for Integrated Circuit Design , 2019, IEEE Journal of Emerging and Selected Topics in Power Electronics.

[5]  Steven L. Garverick,et al.  Extreme temperature 6H‐SiC JFET integrated circuit technology , 2009 .

[6]  Hao Wu,et al.  Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics , 2014, Nature Communications.

[7]  Ying-Yu Chen,et al.  Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  John Gantz,et al.  The Digital Universe in 2020: Big Data, Bigger Digital Shadows, and Biggest Growth in the Far East , 2012 .

[9]  Jean-Pierre Colinge,et al.  Multi-gate SOI MOSFETs , 2007 .

[10]  Ron Dagani,et al.  CARBON-BASED ELECTRONICS , 1999 .

[11]  Lukas Czornomaz,et al.  Towards large size substrates for III-V co-integration made by direct wafer bonding on Si , 2014 .

[12]  Daniel D. Frey,et al.  Statistics of retention failure in the low resistance state for hafnium oxide RRAM using a Kinetic Monte Carlo approach , 2015, Microelectron. Reliab..

[13]  David I. Lewin,et al.  DNA computing , 2002, Comput. Sci. Eng..

[14]  Affan Abbasi,et al.  High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application , 2016 .

[15]  Ole Bethge,et al.  A microprocessor based on a two-dimensional semiconductor , 2016, Nature Communications.

[16]  Gary W. Hunter,et al.  Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions , 2019, IEEE Journal of the Electron Devices Society.

[17]  Y. Sugiyama,et al.  Highly-sensitive InGaAs-2DEG Hall device made of pseudomorphic In0.52A10.48As/In0.8Ga0.2As heterostructure , 1992 .

[18]  Jörg Henkel,et al.  Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance , 2018, IEEE Access.

[19]  T Mizutani,et al.  Relation between conduction property and work function of contact metal in carbon nanotube field-effect transistors , 2006, Nanotechnology.

[20]  Moon J. Kim,et al.  MoS2 transistors with 1-nanometer gate lengths , 2016, Science.

[21]  H. Riel,et al.  Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si , 2015 .

[22]  Gary W. Hunter,et al.  Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions , 2016 .

[23]  Charles M. Lieber,et al.  Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed. , 2008, Nano letters.

[24]  Giovanni De Micheli,et al.  System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits , 2014, JETC.

[25]  Huazhong Yang,et al.  A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System , 2019, IEEE Journal of Solid-State Circuits.

[26]  Yun Shang,et al.  An Optimized Majority Logic Synthesis Methodology for Quantum-Dot Cellular Automata , 2010, IEEE Transactions on Nanotechnology.

[27]  J. Yates,et al.  Band bending in semiconductors: chemical and physical consequences at surfaces and interfaces. , 2012, Chemical reviews.

[28]  埃尔南·卡斯特罗 Accessing memory cells in parallel in a cross-point array , 2014 .

[29]  S. Slesazeck,et al.  The Past, the Present, and the Future of Ferroelectric Memories , 2020, IEEE Transactions on Electron Devices.

[30]  H. Zirath,et al.  Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication , 2017, Scientific Reports.

[31]  Chen Chen,et al.  Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons , 2016, Nature Communications.

[32]  Samaresh Das,et al.  Junctionless nanowire transistor fabricated with high mobility Ge channel , 2014 .

[33]  Ronny Ronen,et al.  CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM , 2019, IEEE Micro.

[34]  W. Lu,et al.  Ge nanowire photodetector with high photoconductive gain epitaxially integrated on Si substrate , 2017 .

[35]  Hongwei Zhu,et al.  Two-dimensional MoS2: Properties, preparation, and applications , 2015 .

[36]  Michael T. Niemier,et al.  The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures , 2020, IEEE Design & Test.