3D floorplan representations: Corner links and partial order
暂无分享,去创建一个
Evangeline F. Y. Young | Ronald L. Graham | Chung-Kuan Cheng | Ilgweon Kang | Daniel Kane | Fang Qiao | Chung-Kuan Cheng | Ilgweon Kang | D. Kane | R. Graham | F. Qiao
[1] Walter S. Scott,et al. The Magic VLSI Layout System , 1985 .
[2] Sheqin Dong,et al. 3D CBL: an efficient algorithm for general 3D packing problems , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..
[3] Yoji Kajitani,et al. The 3 D-Packing by Meta Data Structure and Packing Heuristics , 2000 .
[4] Ting-Ao Tang. Proceedings of the 2005 Asia and South Pacific Design Automation Conference , 2005 .
[5] Sheqin Dong,et al. A Fast 3D-BSG Algorithm for 3D Packing Problem , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[6] Liang Deng,et al. Floorplanning for 3-D VLSI design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[7] Yao-Wen Chang,et al. Temporal floorplanning using the three-dimensional transitive closure subGraph , 2007, TODE.
[8] Dileep A. Divekar. Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools , 1984 .
[9] Sudipta Roy,et al. A new efficient topological structure for floorplanning in 3D VLSI physical design , 2014, 2014 IEEE International Advance Computing Conference (IACC).
[10] Evangeline F. Y. Young,et al. Twin binary sequences: a non-redundant representation for general non-slicing floorplan , 2002, ISPD '02.
[11] Ronald L. Graham,et al. Floorplan representations: Complexity and connections , 2003, TODE.
[12] Yici Cai,et al. Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[13] Jens Lienig,et al. Solution space investigation and comparison of modern data structures for heterogeneous 3D designs , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).
[14] Igor L. Markov,et al. Are floorplan representations important in digital design? , 2005, ISPD '05.
[15] Keisuke Ishihara,et al. A Tree Based Novel Representation for 3D-Block Packing , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Evangeline F. Y. Young,et al. 3-D floorplanning using labeled tree and dual sequences , 2008, ISPD '08.
[17] Chung-Kuan Cheng,et al. Representing topological structures for 3-D floorplanning , 2009, 2009 International Conference on Communications, Circuits and Systems.
[18] Yao-Wen Chang,et al. Temporal floorplanning using the T-tree formulation , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..