Improved timing closure by early buffer planning in floor-placement design flow

Buffer insertion plays an increasingly critical role on circuit performance and signal integrity especially in deep submicron technologies. Buffer insertion stage is very important for buffering efficiency. Early buffer insertion may cause misestimating due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations are fixed and buffer resources may be distributed inappropriately.In this paper, a buffer planning algorithm for floor-placement design flow is presented which creates a map of buffer requirements in various regions of the design at the floorplanning stage based on the statistical distribution of critical paths and enforces the placer to distribute white spaces with respect to the estimated buffer requirement map.Experimental results show that the proposed method improves the performance of experimented circuits with smaller number of buffers and better power consumption compare to conventional methods. Furthermore, power-delay product has been improved considerably, especially for large circuits with a small growth in CPU time.