High speed current-mode signalling for interconnects considering transmission line and crosstalk effects

In this work an efficient approach is used to optimize the power and delay of the global interconnects. The low swing method is optimized and used for various lengths of the global interconnects. Current mode driver and receiver (CMDR) technique are presented. Additionally, a random search algorithm known as Simulated Annealing (SA), improved by an intelligent fashion using a piecewise linear and logarithmic cost function, has been employed to optimize power and delay of the long global interconnects. For verification purposes, several circuits are designed and simulated with Hspice for 0.13 mum technologies. The simulation results show a 25% reduction in power and a 28% reduction in delay with respect to previous designs in the literature.

[1]  Wayne P. Burleson,et al.  Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations , 2005, Sixth international symposium on quality electronic design (isqed'05).

[2]  T. F. Chen,et al.  Segmented bus design for low-power systems , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[3]  N. Tzartzanis,et al.  Differential current-mode sensing for efficient on-chip global signaling , 2005, IEEE Journal of Solid-State Circuits.

[4]  Kwyro Lee,et al.  High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[5]  H. Veendrick.  Digital goes analog , 1998, Proceedings of the 24th European Solid-State Circuits Conference.

[6]  Harry J. M. Veendrick,et al.  High speed current-mode signaling circuits for on-chip interconnects , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[7]  Hui Zhang,et al.  Low-swing interconnect interface circuits , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[8]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.