CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits

CARLOS, a program system for the automated synthesis of random combinational CMOS logic, is described. The input of CARLOS is a specification of a multiple-output Boolean function in the form of a truth table. CARLOS produces an optimized random logic circuit composed of NAND, NOR, and complex gates under the given fan-in and fan-out limitations. The algorithms implemented in CARLOS are based on logic minimization, novel multiple-output multilevel factoring strategies, and recursive technology mapping. The factorization algorithm performs multiple-output synthesis using an algebraic representation of multiple-output Boolean functions. Tests on a large set of examples have shown the efficiency of the synthesis in terms of circuit size as well as computation time. CARLOS is an integral part of a larger CAD system that supports the automatic logic and physical design of finite-state machines under gate-array constraints. >

[1]  Jean-Pierre Dussault,et al.  A High Level Synthesis Tool for MOS Chip Design , 1984, 21st Design Automation Conference Proceedings.

[2]  Stephen Y. H. Su,et al.  Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints , 1971, IEEE Transactions on Computers.

[3]  Nobuaki Kawato,et al.  A Rule-Based Logic Circuit Synthesis System for CMOS Gate Arrays , 1986, DAC 1986.

[4]  Takao Uehara A Knowledge-Based Logic Design System , 1985, IEEE Design & Test of Computers.

[5]  William W. Cohen,et al.  Synthesis and Optimization of Multilevel Logic under Timing Constraints , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Donald L. Dietmeyer,et al.  Logic Design Automation of Fan-In Limited NAND Networks , 1969, IEEE Transactions on Computers.

[7]  Tsutomu Sasao MACDAS: Multi-level AND-OR Circuit Synthesis Using Two-Variable Function Generators , 1986, DAC 1986.

[8]  Daniel L. Ostapko,et al.  MINI: A Heuristic Approach for Logic Minimization , 1974, IBM J. Res. Dev..

[9]  David E. Muller,et al.  Application of Boolean algebra to switching circuit design and to error detection , 1954, Trans. I R E Prof. Group Electron. Comput..