2-bit/Cell Split Gate Flash Memory with Double Gate

We have proposed a 2-bit/cell split gate flash memory device with double gate structure. As well as the separation of the charge storage nodes physically, a supplementary select gate is appended to enhance the programming efficiency by the source-side injection (SSI). Conventional split gate device operation requires 3 gates. In this paper, we show that a device which requires only 2 gates is able to perfectly behave like common split gate, by using a numerical simulator.