Novel Fully Digital-Controlled Point of Load Converter Based on H-bridge DC-DC Converter

Point of load converters (POLs) are key parts in increasing the clock frequency of LSIs and reducing the power consumption of the wiring resistance of the circuit board. In order to suppress the voltage fluctuation due to the voltage drop caused by the wiring resistance or the parasitic inductance, it is necessary to place POLs in the immediate vicinity of the LSI. In order to achieve the ultimate miniaturization of power supply, power supply on chip (power-SoC), which can implement power semiconductor devices, passive components, and control circuits on silicon wafers, has attracted much attention and research interest in recent years (Fig. 1) . Power-SoC has two key challenges. First, it is difficult to apply high-frequency (> 10 MHz) DC-DC converters in pulse width modulation (PWM) control. In order to realize power-SoC, highfrequency switching of several tens MHz is required. Therefore, a control technology other than PWM must be developed. Second, the power capacity per POL is small. When we use the power-SoC, the volume is very small and the power density is high because the passive components are small. Therefore, it operates with high efficiency at a light load, and the efficiency drops considerably at a heavy load. In order to solve these two problems, we proposed a control technique based on parallel connected POLs as shown in Fig. 2 . This control technique only switches the number of working POLs according to the output voltage and does not change the duty ratio. Therefore, this control technique is the open loop type. The proposed control technique can realize high frequency switching and high efficiency operation over a wide load range. Figure 3 shows the control algorithm proposed previously (8) (10) . First, the output voltage is read by an FPGA through an AD converter. Subsequently, the