CIXOB-k: combined input-crosspoint-output buffered packet switch

We propose a novel architecture, a combined input-crosspoint-output buffered (CIXOB-k, where k is the size of the crosspoint buffer) Switch. CIXOB-k architecture provides 100% throughput under uniform and unbalanced traffic. It also provides timing relaxation and scalability. CIXOB-k is based on a switch with combined input-crosspoint buffering (CIXB-k) and round-robin arbitration. CIXB-k has a better performance than a non-buffered crossbar that uses iSLIP arbitration scheme. CIXOB-k uses a small speedup to provide 100% throughput under unbalanced traffic. We analyze the effect of the crosspoint buffer size and the switch size under uniform and unbalanced traffic for CIXB-k. We also describe solutions for relaxing the crosspoint memory amount and scalability for a CIXOB-k switch with a large number of ports.

[1]  Thomas E. Anderson,et al.  High speed switch scheduling for local area networks , 1992, ASPLOS V.

[2]  Nick McKeown,et al.  A practical scheduling algorithm to achieve 100% throughput in input-queued switches , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[3]  Satoshi Nojima,et al.  Integrated Services Packet Network Using Bus Matrix Switch , 1987, IEEE J. Sel. Areas Commun..

[4]  Naoaki Yamanaka,et al.  High-speed ATM switch with input and cross-point buffers , 1993 .

[5]  Nicolas D. Georganas,et al.  Limited intermediate buffer switch modules and their interconnection networks for B-ISDN , 1992, [Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications.

[6]  A. Charny,et al.  On the speedup required for work-conserving crossbar switches , 1998, 1998 Sixth International Workshop on Quality of Service (IWQoS'98) (Cat. No.98EX136).

[7]  Fouad A. Tobagi,et al.  Fast packet switch architectures for broadband integrated services digital networks , 1990, Proc. IEEE.

[8]  Hamid Ahmadi,et al.  A survey of modern high-performance switching techniques , 1989, IEEE J. Sel. Areas Commun..

[9]  Nick McKeown,et al.  A Starvation-free Algorithm For Achieving 100% Throughput in an Input- Queued Switch , 1999 .

[10]  J. Chao.  Saturn: a terabit packet switch using dual round robin , 2000 .

[11]  Nicolas D. Georganas,et al.  16*16 limited intermediate buffer switch module for ATM networks , 1991, IEEE Global Telecommunications Conference GLOBECOM '91: Countdown to the New Millennium. Conference Record.

[12]  R. Rojas-Cessa,et al.  CIXB-1: combined input-one-cell-crosspoint buffered switch , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[13]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[14]  Eiji Oki,et al.  OPTIMA: Scalable, multi-stage, 640-Gbit/s ATM switching system based on advanced electronic and optical WDM technologies , 2000 .

[15]  Mark J. Karol,et al.  Queueing in high-performance packet switching , 1988, IEEE J. Sel. Areas Commun..

[16]  H. T. Mouftah,et al.  Survey of ATM Switch Architectures , 1995, Comput. Networks ISDN Syst..

[17]  Nick McKeown,et al.  The Tiny Tera: A Packet Switch Core , 1998, IEEE Micro.

[18]  H. Jonathan Chao,et al.  On the performance of a dual round-robin switch , 2001, Proceedings IEEE INFOCOM 2001. Conference on Computer Communications. Twentieth Annual Joint Conference of the IEEE Computer and Communications Society (Cat. No.01CH37213).