High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application

Comparison of junctionless and conventional nanowire FETs is presented. Our numerical simulation results suggest that though the junctionless device suffers low drive current due to its accumulation nature, it has an advantage in scalability. Relaxed wire diameter requirement is predicted for the junctionless case. More interestingly, it shows a great potential in ultra-low power subthreshold logic application due to superior speed, as compared with the conventional structure.