An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm

This paper presents efficient hardware architecture for Lempel-Ziv-Welch (LZW) data compression algorithm that can perform both encoding and decoding operations simultaneously using a CAM array. An enhanced CAM cell design has been proposed to achieve search and twofold store operations in single access during regular match operations. The proposed architecture utilizes these enhanced CAM cells to accelerate the implementation of the LZW algorithm. The performance of the proposed design is evaluated using the Corpus benchmarks, where on an average a performance improvement of 53times is achieved when compared to the software approach

[1]  K. Pagiamtzis,et al.  A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme , 2004, IEEE Journal of Solid-State Circuits.

[2]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[3]  Edward J. McCluskey,et al.  A reliable LZ data compressor on reconfigurable coprocessors , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[4]  Chauchin Su,et al.  Hardware efficient updating technique for LZW CODEC design , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[5]  A. J. McAuley,et al.  A reconfigurable content addressable memory , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[6]  Terry A. Welch,et al.  A Technique for High-Performance Data Compression , 1984, Computer.

[7]  Mark R. Nelson,et al.  LZW data compression , 1989 .

[8]  D. Huffman.  A Method for the Construction of Minimum-Redundancy Codes , 1952 .