Elimination of effects due to patterning imperfections in electrical test structures for submicrometer feature metrology

Abstract This paper describes the elimination of a substrate-dependent systematic error that was experienced in prior work on measuring the separation of parallel features with an electrical test structure with total errors less than 10 nm. The test structure was an enhancement of a sliding-wire voltage-dividing potentiometer which scaled the overall test structure geometry to obtain greater sensitivity. It also incorporated features to eliminate adverse effects of voltage tap- and bridge-linewidth scaling. The measurement algorithm that was developed provided the relative separations of sets of features of the 10 nm level. However, absolute measurements were offset by a quantity characteristic of the substrate for which they were extracted. The evidence suggested that these systematic errors were not caused by the primary pattern generation tool. As a result of observations, measurements and simulations, this paper attributes the substrate-characteristic systematic error to an orientation dependence of the quality of replication of certain features of the test structure. An alternative design and measurement algorithm is shown to be able to practically eliminate these errors.