Improved adiabatic pseudo-domino logic family

An improved input-isolation structure for APDL (adiabatic pseudo-domino logic) is proposed. The proposed circuit, IAPDL (improved APDL), provides a higher frequency performance in excess of 1 GHz with simple clock supplies. It is more compact compared with T-APDL (transmission gate-interfaced APDL) and the power dissipation is generally about half that of APDL. HSPICE simulations were performed and the results indicate that a reduction of up to 75% in power dissipation can be achieved compared to conventional CMOS.