RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs

SRAM-based FPGA designs are extremely susceptible to single event upset (SEUs). Since the configuration memory defines which is the circuit an SRAM-based field programmable gate array (FPGA) implements, any change induced by SEUs in the configuration memory may modify drastically the implemented circuit. When such devices are used in safety-critical applications, fault tolerant techniques are needed able to mitigate the effects of SEUs in FPGA's configuration memory. In this paper we present a reliability-oriented place and route algorithm that is able to mitigate the effects of the considered upsets.

[1]  C. Y. Lee.  An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[2]  Luigi Carro,et al.  On the optimal design of triple modular redundancy logic for SRAM-based FPGAs , 2005, Design, Automation and Test in Europe.

[3]  D. Bortolato,et al.  Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  Carl Ebeling,et al.  Placement and routing tools for the Triptych FPGA , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Raoul Velazco,et al.  Radiation test methodology for SRAM-based FPGAs by using THESIC+ , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[6]  M. Caffrey,et al.  Evaluating TMR Techniques in the Presence of Single Event Upsets , 2003 .

[7]  E. Normand.  Single event upset at ground level , 1996 .

[8]  Luigi Carro,et al.  Designing fault tolerant systems into SRAM-based FPGAs , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  A. Paccagnella,et al.  Ion beam testing of SRAM-based FPGA's , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[10]  J. Barth,et al.  Space, atmospheric, and terrestrial radiation environments , 2003 .

[11]  Luigi Carro,et al.  Designing fault-tolerant techniques for SRAM-based FPGAs , 2004, IEEE Design & Test of Computers.

[12]  Michael J. Wirthlin,et al.  The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[13]  Chak-Kuen Wong,et al.  Universal switch modules for FPGA design , 1996, TODE.

[14]  Charles E. Stroud,et al.  BIST-based diagnosis of FPGA interconnect , 2002, Proceedings. International Test Conference.

[15]  D. Bortolato,et al.  Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs” , 2003 .

[16]  A. Candelori,et al.  Heavy ion effects on configuration logic of Virtex FPGAs , 2005, 11th IEEE International On-Line Testing Symposium.

[17]  A. El Gamal,et al.  Architecture of field-programmable gate arrays , 1993, Proc. IEEE.

[18]  Alessandro Paccagnella,et al.  Ion beam testing of ALTERA APEX FPGAs , 2002, IEEE Radiation Effects Data Workshop.

[19]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[20]  Kenneth A. LaBel,et al.  Radiation effects on current field programmable technologies , 1997 .

[21]  Paolo Bernardi,et al.  On the evaluation of SEU sensitiveness in SRAM-based FPGAs , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[22]  Vaughn Betz,et al.  Directional bias and non-uniformity in FPGA global routing architectures , 1996, ICCAD 1996.

[23]  T. P. Ma,et al.  Ionizing radiation effects in MOS devices and circuits , 1989 .

[24]  Michael J. Wirthlin,et al.  SEU mitigation for half-latches in Xilinx Virtex FPGAs , 2003 .

[25]  E. Fuller,et al.  RADIATION TESTING UPDATE, SEU MITIGATION, AND AVAILABILITY ANALYSIS OF THE VIRTEX FPGA FOR SPACE RECONFIGURABLE COMPUTING. , 2000 .

[26]  S. Katkoori,et al.  Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs , 2004, IEEE Transactions on Nuclear Science.