On-chip network resource management design and validation

Designing interconnection networks for systems on-a-chip is getting more complex due to the increasing number and heterogeneity of elements they connect, the variety of technologies adopted to transmit and route information, the performance and cost requirements and constraints they have to satisfy. The complexity of such transmission fabrics gets then closer to that of telecommunication networks. Designers face more and more often the possibility of importing techniques from the classical world of communication networks, and to augment interconnection fabrics with reconfigurable features and dynamic resource management. In order to evaluate such opportunities, they have to be able to simulate the architectures in mind under the most realistic possible conditions. Up to now, the only tools exploited for the simulation of such complex networks have been network simulators. In this paper we consider the possibility of using MPSoC simulation frameworks for the early evaluation of reconfigurable networks-on-chip (NoCs), with the advantage of providing more realistic scenarios and stimuli to the network, and with the aim of obtaining more reliable evaluations.

[1]  José Duato,et al.  A methodology for developing dynamic network reconfiguration processes , 2003, 2003 International Conference on Parallel Processing, 2003. Proceedings..

[2]  Edward A. Lee,et al.  Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..

[3]  Thilo Pionteck,et al.  Applying Partial Reconfiguration to Networks-On-Chips , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[4]  Henk Corporaal,et al.  An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[5]  Patrick Schaumont,et al.  Integrated modeling and generation of a reconfigurable network-on-chip , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[6]  Radu Marculescu,et al.  On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches , 2007, TODE.

[7]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[8]  Camel Tanougast,et al.  CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[9]  Wang Qi,et al.  Simulation and performance evaluation for network on chip design using OPNET , 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

[10]  Sri Parameswaran,et al.  NoCGEN:a template based reuse methodology for Networks On Chip architecture , 2004, 17th International Conference on VLSI Design. Proceedings..

[11]  Kees G. W. Goossens,et al.  Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[12]  Luca Fossati,et al.  ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Ney Laert Vilar Calazans,et al.  MAIA - a framework for networks on chip generation and verification , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[14]  Ahmet T. Erdogan,et al.  Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).