Hardware reuse at the behavioral level

Standard interfaces for hardware reuse are currently defined at the structural level. In contrast to this, our contribution defines the reuse interface at the behavioral register-transfer (RT) level. This promotes direct reuse of functionality and avoids the integration problems of structural reuse. We present an object oriented reuse interface in C++ and show the use of it within two real-life designs.

[1]  Grant Martin Design methodologies for system level IP , 1998, Proceedings Design, Automation and Test in Europe.

[2]  Bill Lin,et al.  Hardware/Software Communication and System Integration for Embedded Architectures , 1997, Des. Autom. Embed. Syst..

[3]  Wolfgang Nebel,et al.  Object-oriented modelling of parallel hardware systems , 1998, Proceedings Design, Automation and Test in Europe.

[4]  Ralph Johnson,et al.  design patterns elements of reusable object oriented software , 2019 .

[5]  Stan Y. Liao,et al.  Using a Programming Language for Digital System Design , 1997, IEEE Des. Test Comput..

[6]  Peter J. Ashenden,et al.  Reuse through genericity in SUAVE , 1997, Proceedings VHDL International Users' Forum. Fall Conference.

[7]  Patrick Schaumont,et al.  A programming environment for the design of complex high speed ASICs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[8]  Gunther Lehmann,et al.  A VHDL reuse workbench , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[9]  Bachir Djafri,et al.  OOVHDL: object oriented VHDL , 1997, Proceedings VHDL International Users' Forum. Fall Conference.

[10]  Wolfgang Ecker,et al.  Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.