Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks

Recent work has shown that monolithic integration of voltage regulators will be feasible in the near future, enabling reduced system cost and the potential for fine-grain voltage scaling (FGVS). More specifically, on-chip switched-capacitor regulators appear to offer an attractive trade-off in terms of integration complexity, power density, power efficiency, and response time. In this paper, we use architecture-level modeling to explore a new dynamic voltage/frequency scaling controller called the fine-grain synchronization controller (FG-SYNC+). FG-SYNC+ enables improved performance and energy efficiency at similar average power for multithreaded applications with activity imbalance. We then use circuit-level modeling to explore various approaches to organizing on-chip voltage regulation, including a new approach called reconfigurable power distribution networks (RPDNs). RPDNs allow one regulator to "borrow" energy storage from regulators associated with underutilized cores resulting in improved area/power efficiency and faster response times. We evaluate FG-SYNC+ and RPDN using a vertically integrated research methodology, and our results demonstrate a 10-50% performance and 10-70% energy-efficiency improvement on the majority of the applications studied compared to no FGVS, yet RPDN uses 40% less area compared to a more traditional per-core regulation scheme.

[1]  Gu-Yeon Wei,et al.  A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS , 2012, IEEE Journal of Solid-State Circuits.

[2]  W.G. Dunford,et al.  A Fully Integrated 660 MHz Low-Swing Energy-Recycling DC–DC Converter , 2009, IEEE Transactions on Power Electronics.

[3]  R. Dennard,et al.  A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 , 2010, 2010 Symposium on VLSI Circuits.

[4]  Taewhan Kim,et al.  DC–DC Converter-Aware Power Management for Low-Power Embedded Systems , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Hai Li,et al.  VSV: L2-miss-driven variable supply-voltage scaling for low power , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[6]  S. Naffziger,et al.  A 90-nm variable frequency clock system for a power-managed itanium architecture processor , 2006, IEEE Journal of Solid-State Circuits.

[7]  Michael Douglas Seeman,et al.  A Design Methodology for Switched-Capacitor DC-DC Converters , 2009 .

[8]  Elad Alon,et al.  Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  R. Harjani,et al.  A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors , 2008, IEEE Journal of Solid-State Circuits.

[10]  David Blaauw,et al.  Limits of Parallelism and Boosting in Dim Silicon , 2013, IEEE Micro.

[11]  Kenichi Okada,et al.  A 0.022mm2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[12]  Stéphan Jourdan,et al.  Haswell: The Fourth-Generation Intel Core Processor , 2014, IEEE Micro.

[13]  Elad Alon,et al.  Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters , 2011, IEEE Journal of Solid-State Circuits.

[14]  Luca P. Carloni,et al.  An integrated four-phase buck converter delivering 1A/mm2 with 700ps controller delay and network-on-chip load in 45-nm SOI , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[15]  Meeta Sharma Gupta,et al.  System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[16]  T. Karnik,et al.  Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[17]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[18]  Anantha Chandrakasan,et al.  Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Xiang Pan,et al.  Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[20]  Zhiyu Zeng,et al.  Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation , 2010, Design Automation Conference.

[21]  J. W. Kolar,et al.  A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS , 2013, 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC).

[22]  Nam Sung Kim,et al.  Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[23]  Naehyuck Chang,et al.  Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[24]  Ramesh Harjani,et al.  Fully integrated on-chip DC-DC converter with a 450x output range , 2010, IEEE Custom Integrated Circuits Conference 2010.

[25]  Gang Huang,et al.  Compact Physical Models for Power Supply Noise and Chip/Package Co-Design of Gigascale Integration , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[26]  Trevor Mudge,et al.  Reevaluating Fast Dual-Voltage Power Rail Switching Circuitry , 2012 .

[27]  Pingqiang Zhou,et al.  Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[28]  Lawrence T. Clark,et al.  An embedded 32-b microprocessor core for low-power and high-performance applications , 2001 .

[29]  Margaret Martonosi,et al.  Techniques for Multicore Thermal Management: Classification and New Exploration , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[30]  A.P. Chandrakasan,et al.  Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering , 2006, IEEE Journal of Solid-State Circuits.

[31]  Tajana Simunic,et al.  Dynamic voltage frequency scaling for multi-tasking systems using online learning , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[32]  Gu-Yeon Wei,et al.  Thread motion: fine-grained power management for multi-core systems , 2009, ISCA '09.

[33]  Christoforos E. Kozyrakis,et al.  Dynamic management of TurboMode in modern multi-core chips , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[34]  Minyi Guo,et al.  AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[35]  Philip T. Krein,et al.  System energy minimization via joint optimization of the DC-DC converter and the core , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[36]  Zhiyi Yu,et al.  A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[37]  Margaret Martonosi,et al.  Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors , 2009, ISCA '09.

[38]  J. Kolar,et al.  A 4.6 W/mm2 Power Density 86% Efficiency On-Chip Switched Capacitor DC-DC Converter in 32nm SOI CMOS , 2012 .

[39]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[40]  Rais Miftakhutdinov,et al.  An Analytical Comparison of Alternative Control Techniques for Powering Next-Generation Microprocessors , 2001 .

[41]  Michael D. Seeman,et al.  A comparative analysis of Switched-Capacitor and inductor-based DC-DC conversion technologies , 2010, 2010 IEEE 12th Workshop on Control and Modeling for Power Electronics (COMPEL).

[42]  M Wens,et al.  A Fully Integrated CMOS 800-mW Four-Phase Semiconstant ON/OFF-Time Step-Down Converter , 2011, IEEE Transactions on Power Electronics.

[43]  John Paul Shen,et al.  Mitigating Amdahl's law through EPI throttling , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[44]  B. Calhoun,et al.  Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[45]  S. Narendra,et al.  A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package , 2005, IEEE Journal of Solid-State Circuits.

[46]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[47]  John Crossley,et al.  A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19W/mm2 at 73% efficiency , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[48]  Alyssa B. Apsel,et al.  Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[49]  Meeta Sharma Gupta,et al.  Voltage emergency prediction: Using signatures to reduce operating margins , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[50]  Marios C. Papaefthymiou,et al.  Utilizing Dark Silicon to Save Energy with Computational Sprinting , 2013, IEEE Micro.