Multicore based highly parallel and flexible framework for HEVC motion estimation

In this work, a highly parallel and flexible framework based on a multicore processor which is especially optimized for computation-intensive execution is proposed to accelerate motion estimation for HEVC. Using multilevel on-chip communication mechanism greatly enhances efficiency and flexibility of data exchange in motion estimation. Experimental results not only validate the feasibility of the framework, but also show that ME achieves 8.5 times speedup comparing to typical frameworks while 16 cores are utilized.

[1]  Yi Li,et al.  A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  David Flynn,et al.  HEVC Complexity and Implementation Analysis , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[3]  Satoshi Goto,et al.  Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC , 2011, IEICE Trans. Electron..

[4]  Gary J. Sullivan,et al.  Overview of the High Efficiency Video Coding (HEVC) Standard , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[5]  Anantha Chandrakasan,et al.  Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine , 2012, 2012 19th IEEE International Conference on Image Processing.