Design of stable SRAM cells based on Schmitt Trigger
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[1] Kaushik Roy,et al. Process variation tolerant SRAM array for ultra low voltage applications , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[2] Varakorn Kasemsuwan,et al. Low voltage adjustable CMOS Schmitt trigger , 2011, 2011 Fourth International Conference on Modeling, Simulation and Applied Optimization.
[3] N. Vallepalli,et al. A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.
[4] Yong-Bin Kim,et al. A 32nm SRAM design for low power and high stability , 2008, 2008 51st Midwest Symposium on Circuits and Systems.
[5] Anna W. Topol,et al. Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
[6] Jan M. Rabaey,et al. Digital Integrated Circuits: A Design Perspective , 1995 .
[7] K. Roy,et al. A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.
[8] O. H. Schmitt,et al. A thermionic trigger , 1938 .