Fast Kerf- and Tester-Compatible Method for RC Characterization of DRAM Memory Cells

A kerf and tester compatible test structure is presented which allows fast and reliable evaluation of resistance and capacitance values of DRAM memory cells. The circuit is realized in a 70nm DRAM process, consumes an area of 795mum times 76mum, and requires six interconnect pads. Using standard electrical measurement equipment, the characterization method reveals resistance and capacitance based on DC current measurements and using ab-initio analytical expressions. Measured results from different lots are shown and compared to the simulated circuit behavior

[1]  D. Schmitt-Landsiedel,et al.  Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages , 1995, Proceedings of International Electron Devices Meeting.

[2]  J.C. Chen,et al.  A simple method for on-chip, sub-femto Farad interconnect capacitance measurement , 1997, IEEE Electron Device Letters.

[3]  J.C. Chen,et al.  An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique , 1996, International Electron Devices Meeting. Technical Digest.

[4]  K. Bowman,et al.  Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance , 2000, IEEE Journal of Solid-State Circuits.