PostscriptTM rendering with virtual hardware

This paper presents the techniques being developed to design a high speed PostScript rendering engine using virtual hardware. The problem of rendering PostScript is decomposed into a series of tasks which can be performed in sequence on one FPGA using virtual hardware.

[1]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[2]  Brad L. Hutchings,et al.  Design methodologies for partially reconfigured systems , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[3]  Richard Cohn,et al.  Portable Document Format Reference Manual , 1993 .

[4]  Satnam Singh,et al.  Virtual hardware for graphics applications using FPGAs , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[5]  Jack Bresenham,et al.  A linear algorithm for incremental digital display of circular arcs , 1977, CACM.

[6]  Brad L. Hutchings,et al.  A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[7]  Uri C. Weiser,et al.  Intel MMX for multimedia PCs , 1997, Commun. ACM.

[8]  Satnam Singh,et al.  Architectural descriptions for FPGA circuits , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[9]  Brad L. Hutchings,et al.  Improving functional density through run-time constant propagation , 1997, FPGA '97.

[10]  Adobe Press,et al.  PostScript Language Reference Manual , 1985 .

[11]  Tom Kean,et al.  A Fast Constant Coefficient Multiplier for the XC6200 , 1996, FPL.

[12]  Jack Bresenham,et al.  Algorithm for computer control of a digital plotter , 1965, IBM Syst. J..

[13]  Patrick Lysaght,et al.  Fast Reconfigurable Crossbar Switching in FPGAs , 1996, FPL.

[14]  Brad Hutchings,et al.  RRANN: the run-time reconfiguration artificial neural network , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.