FPGA-based neuromorphic computing system with a scalable routing network

In this paper, the design and FPGA implementation of a multi-core neuromorphic computing system is presented. This system consists of several computing cores that are connected through an on-chip routing network. Each core is capable of the computation of a 2-layer neural network with a variable number of axon inputs and neurons. This system was built on an Altera FPGA and then examined with a 3-layer RBM and a 5-layer DBN for handwritten digits recognition. Compared to an Intel Core i3 CPU, the multi-core system achieves higher computing speed despite of tiny loss of accuracy.