A Jitter Characterizing BIST with Pulse-Amplifying Technique

A built-in self-test (BIST) circuit for jitter measurement is proposed. The BIST circuit contains an improved cyclic time-to-digital converter (TDC) to achieve 6-ps resolution, and a pulse amplifier (PA) in front of the cyclic TDC to equivalently enhance timing resolution to 0.6 ps. The quantity of jitter is derived by analyzing the digital output codes of the BIST circuit. The input frequency range of the signal-under-test (SUT) is from 200 MHz to 2 GHz for 0.6-ps timing resolution, and from 100 Hz to 2 GHz for 6-ps timing resolution. In addition to the wide input frequency range and fine resolution, the proposed BIST reduces testing time maximally by 95 % in comparison with the conventional BIST circuit based on component-invariant vernier delay line TDC. The presented BIST circuit occupies 0.6 X 0.336 mm2 in a 0.18-um CMOS process.

[1]  J. Kostamovaara,et al.  A low-power CMOS time-to-digital converter , 1995 .

[2]  Gordon W. Roberts,et al.  A CMOS time amplifier for Femto-second resolution timing measurement , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[3]  John A. McNeill.  Jitter in ring oscillators , 1997 .

[4]  Gordon W. Roberts,et al.  A jitter characterization system using a component-invariant Vernier delay line , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Gordon W. Roberts,et al.  Embedded Measurement of GHz Digital Signals With Time Amplification in CMOS , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  J. Kostamovaara,et al.  A CMOS time-to-digital converter with better than 10 ps single-shot precision , 2006, IEEE Journal of Solid-State Circuits.

[7]  K. Karadamoglou,et al.  An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments , 2004, IEEE Journal of Solid-State Circuits.

[8]  K. Nose,et al.  A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling , 2006, IEEE Journal of Solid-State Circuits.

[9]  K. Nose,et al.  A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[10]  Chauchin Su,et al.  BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops , 2008, IEEE Transactions on Instrumentation and Measurement.

[11]  Mani Soma,et al.  Experimental results for high-speed jitter measurement technique , 2004 .

[12]  Jiun-Lang Huang.  On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines , 2006, J. Electron. Test..

[13]  André Ivanov,et al.  Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.

[15]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[16]  Stephan Henzler,et al.  90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.