A method to alleviate hot spot problem in 3D IC

Abstract In three-dimensional integrated circuit, the heat distribution of circuit is irregular and unfixed. Superposition of power consumption in each layer is easy to form hot spots, which seriously affect the performance of the chip. In previous studies, this problem is generally solved by insertion of thermal through silicon via or the reasonable location optimization for TSVs. However, the fixed TSV positioning can't alleviate the dynamic change of hot spots. In this paper, a method to relieve the dynamic hot spots in 3D IC by switching signal in TSV clusters is proposed. When signal is switched in TSV clusters, the variation of the thermal distribution of the chip is analyzed in detail. And we select each signal's TSV cluster transmission path in real time according to the thermal distribution. So that the temperature of the chip can be evenly distributed and the chip can be protected from the hot spots' continuous work. In order to realize the timely signal switching, we designed a TSV cluster switching algorithm and a temperature sensor circuit. The result shows that when a hot spot appears in the circuit which temperature is above 47.67 °C, the signal in the TSV cluster is switched to enable the hot spot gets effectively alleviate.

[1]  Jason Cong,et al.  An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Sung-Mo Kang,et al.  Cell-level placement for improving substrate thermal distribution , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  TingTing Hwang,et al.  Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Jason Cong,et al.  Thermal via planning for 3-D ICs , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[5]  Sachin Sapatnekar,et al.  Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach , 2003, ICCAD 2003.

[6]  Sung Kyu Lim,et al.  Physical design for 3D system on package , 2005, IEEE Design & Test of Computers.

[7]  Sung Kyu Lim,et al.  Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Jinhui Wang,et al.  A novel thermal-aware structure of TSV cluster in 3D IC , 2016 .

[9]  Martin D. F. Wong,et al.  A matrix synthesis approach to thermal placement , 1997, ISPD '97.

[10]  E. Sano,et al.  Characterization of MIS structure coplanar transmission lines for investigation of signal propagation in integrated circuits , 1990 .

[11]  Jing Li,et al.  Efficient Thermal Via Planning for Placement of 3D Integrated Circuits , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[12]  Ligang Hou,et al.  Signal integrity aware TSV positioning , 2012, 2012 Asia-Pacific Symposium on Electromagnetic Compatibility.

[13]  Kia Bazargan,et al.  Placement and routing in 3D integrated circuits , 2005, IEEE Design & Test of Computers.

[14]  Chuan Seng Tan,et al.  Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stack , 2009, 2009 IEEE International Conference on 3D System Integration.