A parallel approach to symbolic traversal based on set partitioning

Binary Decision Diagrams are the state-of-the-art technique for many synthesis, verification and testing problems in CAD for VLSI. Many efforts have been spent to optimize this representation but in many complex applications they still require large amounts of (working) memory and of CPU time. Virtual memory is not a good solution to this problem because, if the working set size for a program is large and memory accesses are random, an extremely large number of page faults significantly modifies software performance.

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