Low-power and high-speed shift-based multiplier for error tolerant applications

We propose a new multiplier design that fulfills the need for low-power circuit blocks used in error-tolerant applications on energy-constrained devices. The design trades accuracy for higher speed, lower energy consumption, and lower transistor count. The average relative error of an N-bit multiplier is modeled as a function of N and saturates at a constant (around 17%) as the multiplier width increases. An 8-bit implementation simulated in HSPICE achieved almost 90% energy savings for a random sample of operands as compared to a conventional parallel multiplier. The design is flexible whereby simple variations to the circuit structure lead to a perfectly accurate multiplier. Tests performed on multimedia applications such as JPEG compression showed a promising outcome.