Verifying and Testing Asynchronous Circuits using LOTOS
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[1] Rocco De Nicola,et al. Three logics for branching bisimulation , 1995, JACM.
[2] George J. Milne,et al. Integrating the verification of timing, performance and correctness properties of concurrent systems , 1998, Proceedings 1998 International Conference on Application of Concurrency to System Design.
[3] Mark Horowitz,et al. Architecture validation for processors , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.
[4] Jan Tretmans,et al. Test Generation with Inputs, Outputs and Repetitive Quiescence , 1996, Softw. Concepts Tools.
[5] Kenneth J. Turner,et al. Protocol-Inspired Hardware Testing , 1999, IWTCS.
[6] David L. Dill,et al. Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.
[7] Wolfgang Rösner. Hardware Design Language , 1989 .
[8] Ganesh Gopalakrishnan,et al. A correctness criterion for asynchronous circuit validation and optimization , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Igor Benko,et al. Parallel Program and Asynchronous Circuit Design , 1995 .
[10] Ronald Leo Christiaan Koymans,et al. A two-level approach to automated conformance testing of VHDL designs , 1997 .
[11] Kenneth J. Turner,et al. Specification and Verification of Synchronous Hardware using LOTOS , 1999, FORTE.