Energy Efficient ARABIC Unicode Reader Design on FPGA

Objectives: This paper proposes an Energy Efficient ARABIC Unicode Reader design on FPGA. Methods/Statistical Analysis: Two types of energy efficient techniques such as Frequency Scaling and FPGA technology scaling have been used to make the device energy and power efficient. In the frequency scaling technique the frequency of device has been varied from 1MHz to 1THz; whereas, in FPGA scaling technique the power consumption of the device at two FPGA technologies(Artix-7 and Virtex-6) has been compared in order to identify the most energy efficient technology at least power consumed frequency. Findings: In this Unicode reader, results have been analyzed using X Power Analyzer. Different types of tables have been created for different range of frequencies showing different power dissipation values. It has been observed that 99.67% of total power can be saved in case of Artix-7 while operating the device at a frequency of 1MHz instead of 1 THz and in case of Virtex-6 98.5% of total power can be saved while operating the device at a frequency of 1MHz instead of 1 THz. So it has been concluded that more amount of power has been dissipated in case of Virtex-6 FPGA technology in which the length of channel is 45nm in comparison to Artix-7 in which length of channel is 28nm. Also it is advisable to operate the device at a low range of frequencies in order to have less power consumption. Application/ Improvements: Conclusions drawn from the analysis will be helpful in making the device more power efficient as compared to the existing ones. It comes out to be a step towards Go-Green Mission in order to serve the humanity.

[1]  Tanesh Kumar,et al.  Low Power Devnagari Unicode Checker Design Using CGVS Approach , 2014 .

[2]  Amanpreet Kaur,et al.  Low voltage digitally control impedance based solar charge controller design on FPGA , 2015, 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom).

[3]  Omolola A. Ogbolumani,et al.  Deployment of Sustainable ICT Infrastructure in Nigeria Vis a Vis the Nation Building , 2015 .

[4]  Amanpreet Kaur,et al.  Energy Efficient Counter Design Using Voltage Scaling on FPGA , 2015, 2015 Fifth International Conference on Communication Systems and Network Technologies.

[5]  Jin-Tak Choi,et al.  The Effectiveness of Visualization System for Virtual Reality Learning , 2015 .

[6]  Amanpreet Kaur,et al.  Capacitance Scaling Based Energy Efficient and Tera Hertz Design of Malayalam Unicode Reader on FPGA , 2015 .

[7]  A. P. Memon Study of Unicode specifications and their implementation in Arabic script languages by designing a multilingual Unicode editor , 2001, Proceedings. IEEE International Multi Topic Conference, 2001. IEEE INMIC 2001. Technology for the 21st Century..

[8]  Tanesh Kumar,et al.  Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network , 2017, Wirel. Pers. Commun..

[9]  Amanpreet Kaur,et al.  Thermal Aware Low Power Universal Asynchronous Receiver Transmitter Design on FPGA , 2014, 2014 International Conference on Computational Intelligence and Communication Networks.

[10]  Amanpreet Kaur,et al.  Energy efficient flip flop design using voltage scaling on FPGA , 2014, 2014 IEEE 6th India International Conference on Power Electronics (IICPE).

[11]  Yasin Kabalci On the Nakagami-m Inverse Cumulative Distribution Function: Closed-Form Expression and Its Optimization by Backtracking Search Optimization Algorithm , 2016, Wirel. Pers. Commun..