Caracterízación eléctrica de nano-mosfets en tecnología SOI

This paper reports about the extensive electrical characterization, with low distortion and greater reliability, of MOSFET devices at nanometric scales with ultra thin Fully Depleted (FD) type architecture on Silicon-On-Insulator (SOI) technology to reduce the short channel effects. The parameters of nMOS type devices of 10x1 μ m 2 gate dimensions with conventional dielectric (SiON) and alternative high-κ dielectric (HfO 2 ) are compared. The extracted parameters are: equivalent oxide thickness (EOT), threshold voltage (V T ) as a function of the SOI body voltage (V B ), transconductance (g m ), maximum transconductance (g m,max ) and its corresponding relation with mobility. The objective is to find if the classic electrical characterization methodology can be applied to the new ultra thin devices overcoming the challenges and physical difficulties imposed by the SOI technology and to demonstrate if the ultra thin devices behavior is similar to conventional MOSFETs. The semiconductor devices analyzed were provided by the IMEC consortium in Belgium and have been characterized in the new nanoelectronics laboratory at Universidad San Francisco de Quito (USFQ) in Ecuador.