A 16-bit, 5MHz multi-bit sigma-delta ADC using adaptively randomized DWA
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This paper describes a 16 bit, 5 MHz analog to digital converter (ADC) chip that advances the state of the art of high speed sigma-delta ADCs by achieving a maximum output data rate of 5 MHz (2.5 MHz input signal bandwidth). The chip, which includes a novel multi-bit digital to analog converter linearization algorithm (AR-DWA) and an on-chip digital decimation filter, gives peak SNR, SFDR, THD of 88.5 dB, 106 dB, -103 dB, respectively.
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