Timing constraints for correct performance

Novel methodology and algorithms for the derivation of timing constraints on all the interconnects were developed and applied to solving layout related timing problems. This methodology is based on detailed information on timing characteristics of cells and nets. A minimax approach for identifying maximal delay bounds for nets which do not violate the timing constraints on any of the logical paths in the design was proposed. An approximation algorithm with proven polynomial time behavior was described. The recursive application of this algorithm results in the distribution of the whole remaining path slacks between the comprising nets, and as a result, zero slack is achieved. The obtained timing bounds were applied to produce layouts free from timing problems.<<ETX>>