Partial-result-reuse architecture and its design technique for morphological operations

This paper proposes a new cost-effective architecture for mathematical morphology named partial-result-reuse (PRR) architecture. For many real-time applications of mathematical morphology, the hardware implementation is necessary; however, the hardware cost of most existing morphology architectures is too high when dealing with large structuring elements. With the partial-result-reuse concept and self-affinity property of general structuring elements, the proposed architecture is more cost-effective and more general than the existing morphology architectures. It can deal with morphological operations with arbitrary structuring elements and can be used for other semi-group operations, and only 2[log/sub 2/n] comparators are needed for n/spl times/n structuring elements. Simulation shows that this architecture can dramatically reduce the hardware cost of morphological operations with all kinds of structuring elements.

[1]  Jean Serra,et al.  Image Analysis and Mathematical Morphology , 1983 .

[2]  Myung Hoon Sunwoo,et al.  A new cost-effective morphological filter chip , 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

[3]  Ioannis Pitas,et al.  Fast computation of a class of running filters , 1998, IEEE Trans. Signal Process..

[4]  Sun-Yuan Kung,et al.  A Linear Systolic Array for Real-Time Morphological Image Processing , 1997, J. VLSI Signal Process..

[5]  Liang-Gee Chen,et al.  Efficient video segmentation algorithm for real-time MPEG-4 camera system , 2000, Visual Communications and Image Processing.

[6]  Theodora A. Varvarigou,et al.  Fast Implementation of Binary Morphological Operations on Hardware-Efficient Systolic Architectures , 2000, J. VLSI Signal Process..

[7]  Ioannis Pitas,et al.  Fast algorithms for running ordering and max/min calculation , 1989 .

[8]  R. W. Brodersen,et al.  Architectures and design techniques for real-time image-processing IC's , 1987 .

[9]  Jaakko T. Astola,et al.  Improving Gil-Werman Algorithm for Running Min and Max Filters , 1997, IEEE Trans. Pattern Anal. Mach. Intell..

[10]  Michael Werman,et al.  Computing 2-D Min, Median, and Max Filters , 1993, IEEE Trans. Pattern Anal. Mach. Intell..

[11]  Jhing-Fa Wang,et al.  A data-reuse architecture for gray-scale morphologic operations , 1992 .