A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology

This paper presents a configurable TX driver with 4-tap pre-emphasis to reduce the inter-symbol-interference (ISI) in high-speed transmission backplane, which is based on the FIR filter. The number of the tap, the selection of the main tap, the selection of the equalization approaches used in each tap and the coefficient of each tap all can be configured according to the particular channel conditions and the need of the receiver's equalizer, and the simulation result shows how the TX driver can reshape a signal based on the settings of the configurable ports. The design was implemented using 65nm CMOS technology. And HSPICE simulation results show that its line rates can be from 100 Mb/s to 3.75Gb/s.

[1]  Bei Liang,et al.  The structure design of MOS current mode logic adder , 2012, 2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT).

[2]  K. R. Lakshmikumar,et al.  High-speed serial transceivers for data communication systems , 2001, IEEE Commun. Mag..

[3]  Feng Zhang,et al.  A 5 Gb/s multi-mode transmitter with de-emphasis for PCI Express 2.0/USB 3.0 , 2014 .

[4]  Jian Gao,et al.  A 6.25Gbps Feed-forward Equalizer in 0.18μm CMOS Technology for SerDes , 2012, 2012 International Conference on Wireless Communications and Signal Processing (WCSP).

[5]  Chulwoo Kim,et al.  A 3 Gb/s transmitter with a tapless pre-emphasis CML output driver , 2014 .

[6]  Markus Appel,et al.  Low-power design methodology for CML and ECL circuits , 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[7]  Ran Ginosar,et al.  Asynchronous Current Mode Serial Communication , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Miao Li,et al.  A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology , 2005, ASP-DAC '05.