Detecting state coding conflicts in STGs using integer programming
暂无分享,去创建一个
[1] Jeffrey D. Ullman,et al. Introduction to Automata Theory, Languages and Computation , 1979 .
[2] Amir Pnueli,et al. Applications of Temporal Logic to the Specification and Verification of Reactive Systems: A Survey of Current Trends , 1986, Current Trends in Concurrency.
[3] Tam-Anh Chu,et al. Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .
[4] Costas S. Iliopoulos. Worst-Case Complexity Bounds on Algorithms for Computing the Canonical Structure of Infinite Abelian Groups and Solving Systems of Linear Diophantine Equations , 1989, SIAM J. Comput..
[5] Hugo De Man,et al. Optimized synthesis of asynchronous control circuits from graph-theoretic specifications , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[6] R. BurchJ.,et al. Symbolic model checking , 1992 .
[7] Luciano Lavagno,et al. A unified signal transition graph model for asynchronous control circuit synthesis , 1992, ICCAD.
[8] Hugo De Man,et al. Optimized synthesis of asynchronous control circuits from graph-theoretic specifications , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Kenneth L. McMillan,et al. Symbolic model checking: an approach to the state explosion problem , 1992 .
[10] Kenneth L. McMillan,et al. Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits , 1992, CAV.
[11] Evelyne Contejean. Solving Linear Diophantine Constraints Incrementally , 1993, ICLP.
[12] Kay Soon Low,et al. Token Ring Arbiters: An Exercise in Asynchronous Logic Design with Petri Nets , 1995 .
[13] Alexandre Yakovlev,et al. Checking signal transition graph implementability by symbolic BDD traversal , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[14] Evelyne Contejean,et al. Complete Solving of Linear Diophantine Equations and Inequations without Adding Variables , 1995, CP.
[15] Manuel Silva Suárez,et al. Linear Algebraic and Linear Programming Techniques for the Analysis of Place or Transition Net Systems , 1996, Petri Nets.
[16] Luciano Lavagno,et al. A unified signal transition graph model for asynchronous control circuit synthesis , 1996, Formal Methods Syst. Des..
[17] Sérgio Vale Aguiar Campos,et al. Symbolic Model Checking , 1993, CAV.
[18] Wolfgang Reisig,et al. Lectures on Petri Nets I: Basic Models , 1996, Lecture Notes in Computer Science.
[19] Luciano Lavagno,et al. Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .
[20] Jordi Cortadella,et al. Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[21] Luciano Lavagno,et al. Complete state encoding based on the theory of regions , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[22] A Yakovlev,et al. Design and Evaluation of Two Asynchronous Token Ring Adapters , 1997 .
[23] Alexei Semenov. Verification and synthesis of asynchronous control circuits using petri net unfoldings , 1997 .
[24] Stephan Melzer,et al. Deadlock Checking Using Net Unfoldings , 1997, CAV.
[25] Evelyne Contejean,et al. Avoiding Slack Variables in the Solving of Linear Diophantine Equations and Inequations , 1997, Theor. Comput. Sci..
[26] Stephan Melzer. Verifikation verteilter Systeme mittels linearer- und Constraint-Programmierung , 1998 .
[27] Alexandre Yakovlev. Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets , 1998, Formal Methods Syst. Des..
[28] Luciano Lavagno,et al. Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings , 1998, Proceedings 1998 International Conference on Application of Concurrency to System Design.
[29] Keijo Heljanko. Using Logic Programs with Stable Model Semantics to Solve Deadlock and Reachability Problems for 1-Safe Petri Nets , 1999, Fundam. Informaticae.
[30] Montek Singh,et al. A Power-Efficient Duplex Communication System , 2000 .
[31] Maciej Koutny,et al. LP Deadlock Checking Using Partial Order Dependencies , 2000, CONCUR.
[32] Anna Philippou,et al. Tools and Algorithms for the Construction and Analysis of Systems , 2018, Lecture Notes in Computer Science.
[33] Alexander B. Smirnov,et al. Towards synthesis of monotonic asynchronous circuits from signal transition graphs , 2001, Proceedings Second International Conference on Application of Concurrency to System Design.
[34] Carlos Delgado Kloos,et al. Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[35] Walter Vogler,et al. An Improvement of McMillan's Unfolding Algorithm , 2002, Formal Methods Syst. Des..