FPGA Implementation of Single Bit Error Correction using CRC

Transferring data between two points is very essential, also the accuracy of the transferred data is vital for some critical applications, but an error during the transmission of data is very common. The Cyclic Redundancy Check (CRC) method is generally used for error detection and correction. In this paper, we have proposed a new technique for error detection and correction in case of CRC-16, which is hardware optimized and works at relatively higher frequency and speed. In the proposed method, it is possible to detect the exact place of single bit error and correct them using minimum hardware. This method involves no look tables and hence is memory efficient. This paper focuses on effective implementation of this method on FPGA.

[1]  H. Jonathan Chao,et al.  The ATM Layer Chip: An ASIC for B-ISDN Applications , 1991, IEEE J. Sel. Areas Commun..

[2]  W. W. PETERSONt,et al.  Cyclic Codes for Error Detection * , 2022 .

[3]  Tenkasi V. Ramabadran,et al.  A tutorial on CRC computations , 1988, IEEE Micro.

[4]  Neil W. Bergmann,et al.  Single bit error correction implementation in CRC-16 on FPGA , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[5]  Les Check,et al.  Fifth International Conference , 1978 .

[6]  Giuseppe Patanè,et al.  Parallel CRC Realization , 2003, IEEE Trans. Computers.

[7]  Charles A. Zukowski,et al.  High-speed parallel CRC circuits in VLSI , 1992, IEEE Trans. Commun..

[8]  Ahmad Khademzadeh,et al.  Double Bits Error Correction Using CRC Method , 2009, 2009 Fifth International Conference on Semantics, Knowledge and Grid.

[9]  葛宁,et al.  CRC Look-up Table Optimization for Single-Bit Error Correction , 2007 .

[10]  Yun Pan,et al.  CRC Look-up Table Optimization for Single-Bit Error Correction , 2007 .