Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput

Traditionally, the communication in neuromorphic VLSI systems has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of neuron pulses. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols. We give a live demonstration of a packet based synchronous serial AER infrastructure presented in a recent paper [1], which handles the complete off-wafer communication and configuration for a newly developed waferscale neuromorphic system [2]1, operating at a factor of 104 faster than biological real-time. Pulse packets are routed from the host PC via Gbit Ethernet to an FPGA board (see Fig. 1), which forwards them to 4 purpose designed Digital Network ASICs (DNCs) on the same board. The DNCs buffer and sort the pulses, implementing 32 2GBit/s Low Voltage Differential Signaling (LVDS) interfaces to the neuromorphic circuits on the wafer. Pulse communication to other wafers is done via an FPGA-FPGA communication using 10Gbit/s Aurora links.