Design planning for high-performance ASICs

Design planning is emerging as a solution to some of the most difficult challenges of the deep-submicron VLSI design era. Reducing design turnaround time for extremely large designs with ever-increasing clock speeds, while ensuring first-pass implementation success, is exhausting the capabilities of traditional design tools. To solve this problem, we have designed and implemented a hierarchical design planning system that consists of a tightly integrated set of design and analysis tools. The integrated run-time environment, with its rich set of hierarchical, timing-driven design planning and implementation functions, provides an advanced platform for realizing a variety of ASIC and custom methodologies. One of the system's particular strengths is its tight integration with an incremental, static timing engine that assists in achieving timing closure in high-performance designs. The design planner is in production use at IBM internal and at external ASIC design centers.

[1]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[2]  Daniel Brand,et al.  BooleDozer: Logic synthesis for ASICs , 1996, IBM J. Res. Dev..

[3]  S. V. Venkatesh.  Hierarchical timing-driven floorplanning and place and route using a timing budgeter , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[4]  Habib Youssef,et al.  Timing constraints for correct performance , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[6]  Wing K. Luk,et al.  A fast physical constraint generator for timing priven layout , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  David J. Hathaway,et al.  Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology , 1997, J. VLSI Signal Process..

[8]  Kimberly Ryan,et al.  Cadence Design Systems Inc. , 1993 .

[9]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  P.R. O'Brien,et al.  Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[11]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .